The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor device having buffers for buffering and outputting an input signal.
Generally, semiconductor devices, including Double Data Rate SDRAM Synchronous Dynamic Random Access Memory (DDR SDRAM), perform write and read operations in response to a data signal, an address signal, and an external command signal from an external chipset. These signals are usually buffered by an input buffer provided within the semiconductor device and then inputted to various elements therein.
FIG. 1 is a circuit diagram for explaining a conventional buffer.
Referring to FIG. 1, the conventional buffer includes a signal input unit 110, an activation unit 130, and a current source unit 150.
The signal input unit 110 is for receiving a reference voltage V_REF and an input signal IN, and is provided with a first NMOS transistor NM1 for receiving the reference voltage V_REF via its gate, and a second NMOS transistor NM2 for receiving the input signal IN via its gate. Here, the reference voltage V_REF generally has a ½ level of a power supply voltage VDD, and is supplied as an internal power supply voltage generated from it.
The activation unit 130 is for activating the signal input unit 110 in response to an activation signal EN, and is provided with a third NMOS transistor NM3 for receiving the activation signal EN via its gate.
The current source unit 150 is for driving an output terminal OUT based on the reference voltage V_REF and the input signal IN, and is provided with first and second PMOS transistors PM1 and PM2.
Hereinafter, the operation of the general buffer will be briefly described. For illustration purposes, it is assumed that the buffering operation of the buffer is activated when the activation signal EN is activated to logic ‘high’.
As such, with the buffer being activated, when the input signal IN is logic ‘high’, i.e., the input signal IN has a higher voltage level than the reference voltage V_REF, Vgs of the second NMOS transistor NM2 becomes larger than Vgs of the first NMOS transistor NM1. That is, the degree to which the second NMOS transistor NM2 is turned on becomes larger than the degree to which the first NMOS transistor NM1 is turned on. Thus, a voltage level of the output terminal OUT becomes gradually lower.
On the other hand, when the input signal IN is logic ‘low’, i.e., the input signal IN has a lower voltage level than the reference voltage V_REF, Vgs of the first NMOS transistor NM1 becomes larger than Vgs of the second NMOS transistor NM2. That is, the degree to which the first NMOS transistor NM1 is turned on becomes larger than the degree to which the second NMOS transistor NM2 is turned on. Thus, a voltage level of the drain terminal of the first NMOS transistor NM1 becomes lower, and a voltage level of the gate terminal of the second PMOS transistor MP2 becomes also lower. Accordingly, a voltage level of the output terminal OUT becomes gradually higher. As a result, the general buffer lowers a voltage level of the output terminal OUT when a voltage level of the input signal IN is higher than the reference voltage V_REF, and raises a voltage level of the output terminal OUT when a voltage level of the input signal IN is lower than the reference voltage V_REF.
Meanwhile, the level of the power supply voltage applied to the semiconductor device may vary depending on chipset used, and the semiconductor device should be designed so that it may perform a desired operation even at various levels of the power supply voltage VDD. That is, the semiconductor device should have a wide range of operations that depend on levels of the power supply voltage VDD. However, existing buffers have difficulties in generating a stable output signal that corresponds to the input signal IN since its operation state varies with characteristics of transistors, regardless of a level of the power supply voltage VDD.
In general, the PMOS transistor and NMOS transistor have a current-driving capacity that varies depending on a level of the power supply voltage VDD. Specifically, the PMOS transistor and NMOS transistor have the following characteristics: if the power supply voltage VDD has a relatively high level, the PMOS transistor has a surplus current-driving capacity; and if the power supply voltage VDD has a relatively low level, the NMOS transistor has a deficient current-driving capacity. This characteristic causes a variation in the duty rate of the output signal from the buffer. Therefore, the existing buffer of such structure varies the duty rate of the output signal depending on a level of the power supply voltage VDD, i.e., causes generation of distortion, which acts as a factor that degrades the performance and reliability of the semiconductor device. Particularly, this problem becomes more serious if noise occurs in the reference voltage V_REF which is the internal power supply voltage.